1. Field of the Invention
This invention relates to controllers for microcomputers and, more particularly, to integrated circuit chip core logic system controllers for minimizing power consumption by a microprocessor in a laptop computer.
2. Prior Art
With the advent of smaller computer systems, such as lap top computers, it has become increasingly important to minimize power consumed by each component of the system.
One area in a lap top computer where power is consumed is in the central processing unit (CPU). Even microprocessor CPUs on integrated circuit chips, such as the Intel 286 and 386 microprocessors, consume appreciable amounts of power. Each time a clock pulse occurs, logic in the CPU consumes power and power consumption is roughly proportional to the frequency of the CPU clock.
CPUs spend a large percentage of the time in idle loops waiting for input/output (I/O) operations to complete and for operator inputs. Therefore, reducing CPU clock speed during periods of CPU inactivity or of low activity, and during I/O operations which do not require high clock frequencies, can result in substantial reduction in power consumption.
The magnitude of clock duty cycle, or the length of time the clock pulse is present, also effects power consumption. During a clock pulse, power is consumed and therefore in some applications, it is desirable to minimize the magnitude of clock pulse duty cycle for minimizing power consumption.
Although it is desirable to minimize frequency and, in some situations, magnitude of clock pulse duty cycle, there are constraints in the system which must be met. For example, when data is being communicated between I/O devices and other parts of the system, it is desirable to operate the CPU at high frequency so that the user does not wait an undesirable length of time for the operation to be completed. However, some types of CPUs cannot operate with as high a clock frequency as other CPUs, and some circuits require larger clock pulse duty cycle for reliable operation.
Also standard system controllers are used which control a variety of CPUs and I/O devices. Therefore, there is a need for an improved clock pulse generating system in a microcomputer system which allows the system designer, or possibly the system user, to select optimum clock frequency and optimum duty cycle. Also, it is desired that the clock pulse generating system be incorporated in a standard system controller useful with a variety of CPUs and I/O devices.
Prior art computer systems are known and have been proposed for reducing clock frequency and for altering clock duty cycle. By way of example, calculators are known where during arithmetic mode, the calculator is clocked at a high frequency, but during display mode, frequency of the clock is reduced to minimize power consumption. In other calculators, power is reduced by using a high frequency (or full speed) clock during execute mode, a lower frequency during display mode, and an even lower frequency during a display inhibit mode.
It is also known to vary the clock pulse duty cycle with changes in clock frequency. That is, there is a different duty cycle for each frequency of clock. Thus, duty cycle is fixed for a given frequency.
Microprocessor systems are also known where the CPU clock is normally at a low frequency or speed, but momentarily speeds up to a higher frequency in response to an interrupt or other condition in the system. In this manner, the clock to the CPU is at a low frequency during periods of inactivity or low activity in the system, but momentarily switches to a high frequency and therefore a higher speed during periods of high activity. By way of example, momentary speedup occurs responsive to interrupts from such input/output devices as hard disks, floppy disks, mouse input devices, keyboards or video controllers. Systems are also known where the speedup is timed so that the momentary speedup terminates after a time interval corresponding to the type of interrupt that initiates the speedup.
Other computer systems are known which inhibit clock signals or reduce the frequency of the clock signals during periods of inactivity or low activity in the system, and then resume normal clock frequency response to interrupts generated in the system.
Microcomputer systems are also known which vary the frequency of the clock to the CPU responsive to the actuation of a switch from a system panel or under control of a computer program or system hardware.
However, a need exists for further reducing the amount of power consumed by the CPU in a microcomputer system, and at the same time providing flexibility to the system designer or user in selecting clock frequency and clock duty cycles, and incorporating these features into a standard system controller chip.
Systems are also known which conserve power in a microcomputer system by shutting off power simultaneously to the CPU and the rest of the system, leaving only those portions of the system which detect power-resume demands active. However, when the entire system is powered down, it takes a long time for the system to resume, causing delays in response which is undesirable to the user. In addition, there are periods of time when the I/O portion of the system is active when the CPU is inactive. By way of example, the I/O portion of the system may be transferring data to a printer or to a display unit, or information may be in the process of being transferred between hard or floppy disk drives and RAM memory. Because of the advent of smart controllers which handle these operations independently of the CPU, the transfer of data may be going on independently of the CPU. As a result, the CPU may be idle a substantial portion of the time. An example of where this may occur is during a word processing operation where a keyboard operator can only input a character at the rate of fractions of a second, whereas the CPU operates in microseconds. The CPU may be waiting a substantial portion of the time for the operator to enter data while nothing is going on in the CPU, and therefore power is being consumed by the CPU needlessly while it is waiting for the next entry from the keyboard. Thus, recognizing the fact that the CPU is a major source of power consumption and yet, because of the speed at which the CPU operates, there are substantial periods of time during which the CPU is actually idling, there is a need to power down the CPU alone and to do so transparently to the user.
As part of the manufacturing process of CMOS circuitry, such as that employed in the above-referenced Intel CPUs and the controller chips 10, 26, and 28 of FIG. 1, a diode circuit is connected to each of the input and output pins for preventing damage to the circuitry from static charge due to handling during the manufacturing process. These diode circuits remain in the circuits when installed in the system.
A problem created by powering down the CPU while the rest of the system is operational is that after power-down, the diodes may cause the CPU to continue to draw power due to signals from the other circuits in the system even though power to the CPU itself has been shut down.
Additionally, such signals may cause the diodes in the diode circuits to be driven into a saturation and latch-up condition such that the inputs to the CPU may be latched up which prevents the CPU from operating even after power is resupplied. In order to unlatch the inputs, it will be necessary to shut off power and then turn power back on to the entire system, which is not desirable.
A further problem is encountered when the CPU is in the process of being powered down while the rest of the system is operational. When power to the CPU is in the process of being shut down, signals may be provided from the CPU to the system controller and I/O controllers which will be erroneously interpreted as valid signals, causing undesirable effects.
One type of microprocessor, by way of example the Intel 80C 286, can be disabled to reduce power consumption by shutting off the clock. This type of microprocessor will retain the states of its registers even though the clock has been disabled. Other types of microprocessors, such as the Intel 80286 and 80386SX, cannot be disabled by shutting off their clocks. To power down this latter type of microprocessor, it is necessary to store the contents of the registers in RAM 30, then shut off power to the microprocessor so that when power is restored, the content of the registers can be restored from the RAM to CPU, enabling the CPU to continue on from the point where power down occurred. Programs for storing the contents of the registers from the microprocessor to RAM and for restoring the content of the registers after power up are well known in the art.
These and other problems and disadvantages of existing systems are overcome with the present invention.